1. Field of the Invention
The present invention relates generally to synchronous semiconductor memory devices which input and output signals in synchronization with a clock, more particularly, to SDRAMs (synchronous random access memories) having input circuits with reduced power consumption.
2. Description of the Related Art
Since DRAM is of a high storage density but consumes a large amount of power compared with SRAM, reduction in power consumption has been demanded.
FIG. 9 is a wiring diagram between a SDRAM controller 10 and a plurality of SDRAMs 11 to 14.
The SDRAM controller 10 decodes the higher order 2-bits of an address provided thereto to produce chip select signals *CS1 to *CS4, and further not only divides the address except the higher order 2 bits into row and column addresses (ADDR) to perform time-division multiplex, but also generates the row address strobe signal RAS and the column address strobe signal CAS in relation to the row and column addresses. The RAS and CAS signals constitute a multi-bit command CMD together with the write enable signal WE. The SDRAM controller 10 sets the clock enable signal CKE high, which is used for generating an internal clock through an AND operation with an external clock CLK, prior to selection of one of SDRAMs 11 to 14.
The SDRAMs 11 to 14 are connected to a microprocessor not shown through the SDRAM controller 10. The chip select signal outputs *CS1 to *CS4 of the SDRAM controller 10 are respectively connected to the chip select signal inputs *CS of the respective SDRAMs 11 to 14, and the outputs of the external clock CLK, command CMD, DATA, address ADDR and clock enable signal CKE of the SDRAM controller 10 are commonly connected to corresponding terminals of the SDRAMs 11 to 14.
When the signals *CS1 to *CS4 are all high and thereby all the SDRAMs 11 to 14 are not selected, the clock enable signal CKE is set low to stop the internal clock in each of the SDRAMs 11 to 14, whereby the input circuits that synchronizes an input with the internal clock becomes deactivate, resulting in reducing consumption of power in each of the SDRAMs 11 to 14.
However, as shown in FIG. 10 for example, when only the SDRAM 11 of the SDRAMs 11 to 14 is selected by setting only the chip select signal *CS1 to low while the signals *CS2 to *CS4 are kept high, power is wasted in the non-selected SDRAMs 12 to 14 since the clock enable signal CKE is set high prior to the selection of the SDRAM 11 and thereby the internal clocks in the SDRAMs 12 to 14 operate and thus the input circuits thereof are activated.
In order to avoid this inconvenience, if independent clock enable signals are provided to the respective SDRAMs 11 to 14, the number of interconnections increases and a configuration of wiring becomes complicated.